Everything runs on somebody else’s wafer

There is a widespread belief that the AI industry is a software industry. It is not. It is a manufacturing industry with a software interface, and every constraint that matters is physical: how many wafers a fab can start, how many stacks of memory can be bonded to a processor, how many megawatts a site can draw.

The stack, from sand to invoice

A frontier accelerator passes through a chain in which almost every link is a near-monopoly.

Design. A handful of companies design AI processors. One of them owns the software ecosystem that most researchers write against, which is the real product. CUDA is nineteen years old and is the reason a technically competitive rival chip still loses time on porting.

Lithography. Extreme ultraviolet machines, which pattern the smallest features, come from exactly one manufacturer in the Netherlands. Each machine costs in the region of two hundred million and the annual output is measured in dozens. This is the narrowest point in the entire world economy that almost nobody outside the industry can name.

Manufacturing. The most advanced logic nodes are made in Taiwan, with South Korea close behind and new capacity being built in the United States, Japan and Germany at higher cost. Concentration here is the reason chip supply is a foreign policy subject.

Memory and packaging. An accelerator is useless without memory fast enough to feed it. HBM stacks are bonded next to the processor in advanced packaging, and packaging capacity, not wafer capacity, has repeatedly been the actual limit on how many accelerators exist.

Why memory keeps being the bottleneck

A large model is mostly a very big pile of numbers that must be read for every token generated. The processor can multiply far faster than memory can supply data, so real throughput is set by memory bandwidth, not by peak arithmetic. That is why each generation stacks more HBM at higher bandwidth, and why a shortage of memory stacks stops accelerator shipments even when wafers are available.

It is also why inference cost per token falls in steps rather than smoothly. A generation that doubles bandwidth roughly halves cost; one that only improves arithmetic does much less in practice.

The challengers and their real problem

Three groups try to break the position. Rival merchant chip vendors compete on price and memory capacity and are gaining in inference, where software lock-in matters less than in training. Hyperscalers design their own accelerators, which are cheaper per unit of their own workload and never have to win a benchmark against anyone. Startups build architectures optimised for one thing, usually fast inference of transformer models.

None of them is short of good silicon. What they are short of is the decade of libraries, kernels, compilers and documented behaviour that makes a chip usable on the day it arrives. The lesson of the last three years is that porting cost is a real cost, and that it falls fastest where the workload is simple and repetitive.

What the DeepSeek moment taught

In January 2025 a reasoning model trained for a reported fraction of the expected cost briefly erased hundreds of billions from chip valuations. The market read it as a demand shock: if models are cheaper to train, fewer chips are needed. The subsequent two years suggested the opposite. Cheaper capability increased use, use is inference, and inference consumes more total compute than training ever did.

The economically useful version of the lesson is this: efficiency gains in a fast-growing market raise total consumption. That is not a law, but it has held so far.

The geography risk, stated plainly

A significant share of advanced logic is made on one island with a contested political status, and the equipment that makes it comes from one company in one country. New fabs elsewhere reduce that concentration slowly and at a cost premium, because a fab takes years and a trained workforce takes longer. Anyone modelling the AI industry without a line for this is modelling the good case.

What to watch

Watch advanced packaging capacity announcements, which predict accelerator supply better than wafer announcements do. Watch memory pricing, which is where shortages show first. And watch whether a major model provider ships a frontier model trained entirely on non-market-leading silicon, because that would be the first real crack in the software moat.